A widely-used self-biased delay line is described in U.S. Pat. No. 5,772,037 and in John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Technique”, IEEE JSSC VOL. 31, No 11, November 1996, pp. 1723-1732 (hereinafter “Maneatis”). The self-biased delay line described in Maneatis apparently offers a number of advantageous features, such as high noise immunity, wide frequency range and low phase offset. The self-biased delay line uses a differential delay stage (also known as a “delay element”) with a linearized, i.e., resistor-like, MOS-transistor load chain (see FIG. 4 in U.S. Pat. No. 5,727,037) and a bias voltage generator (FIG. 3 in U.S. Pat. No. 5,727,037) for controlling signal propagation delay time of the delay element.
While the self-biased delay line described in Maneatis provides superior performance, the self-biased delay line described in Maneatis may be improved by reducing power consumption, reducing sensitivity to operating conditions and reducing sensitivity to variation in process parameters.